1. Field of the Invention
The present invention relates to an output buffer circuit to be loaded in a semiconductor integrated circuit device, and particularly to an output buffer circuit in which the output transistors are divided.
2. Description of the Related Art
Conventionally, such types of output buffer circuits in which the output transistors are divided have been proposed variously. FIG. 1 is a circuit diagram showing an example of a conventional output buffer circuit. As shown in FIG. 1, a conventional output buffer circuit 500 comprises an output transistor section 510 and an inverter 540,550. The output transistor section 510 comprises an inverter 520 and an inverter 530 connected in parallel. The inverter 520 comprises a PMOS transistor (hereinafter referred to as a PMOS) 521 and a NMOS transistor (hereinafter referred to as a NMOS) 522 having channel widths which satisfy a desired driving capability. Also, the inverter 530 comprises a PMOS 531 and a NMOS 532. The channel widths of the PMOS 531 and the NMOS 532 are narrower than those of the PMOS 521 and the NMOS 522. Furthermore, an input terminal of the inverter 520 is connected to an output terminal N504 of the inverter 540, and an input terminal of the inverter 530 is connected to an output terminal N505 of the inverter 550.
Both of the output terminals of the inverters 520, 530 are connected to an output terminal N503 of the output buffer circuit 500. Also, both of the input terminals of the inverters 540, 550 which drive the inverters 520, 530, respectively, are connected to an input terminal N2 of the output buffer circuit 500. Furthermore, the inverters 540, 550 consist of transistors having generally the same sizes.
Also, an example of another conventional output buffer circuit is disclosed in Japanese Patent Publication Laid-Open No. Hei 11-191729 (hereinafter referred to as the prior art). FIG. 2 is a circuit diagram showing an output buffer circuit disclosed in the prior art. As shown in FIG. 2, transistors PMOS 624a, 626a and NMOS 624b, 626b of output final stages divided into at least two are provided in an output buffer circuit 610 disclosed in the prior art. Also, a transistor PMOS 618a for current-voltage limiting is provided between a gate of the PMOS 624a and a gate of the PMOS 626a, and a transistor NMOS 618b for current-voltage limiting is provided between a gate of the NMOS 624b and a gate of the NMOS 626b. Also, driving circuits 616a, 616b for driving the PMOS 624a and the NMOS 624b respectively, in response to potential of an internal signal line 632 are connected to each gate of the PMOS 624a and the NMOS 624b. In addition, gates of the transistors PMOS 626a, NMOS 626b are connected with potential compensation circuits 622a, 622b for compensating the potential of the gate thereof.
In the output buffer circuit 610, when each transistor of the output final stage becomes ON, the driving circuits 616a, 616b drive a gate end of one transistor of the output final stage and at the same time, drive a gate end of another transistor of the output final stage via the transistor for current-voltage limiting, thereby controlling the slew rate of current to suppress the generation of noise and perform high speed operation.
In the conventional output buffer circuit structure in general, for example, if the slew rate standard becomes strict, as in an output buffer circuit for PCI (Peripheral Component Interconnect), then fluctuation in the manufacturing process can have a great effect, and it is very difficult to satisfy the slew rate standard according to conditions such as temperature, power supply voltage, etc.
For example, in the above described output buffer circuit 500 shown in FIG. 1, when adjustment of the slew rate of the signal of the output terminal N503 is desired, it is necessary to blunt the output waveforms of the inverters 540, 550. However, if the output waveforms of the inverters 540, 550 become blunt, then the influence on the output waveforms of the inverters 540, 550 becomes great when a channel length L and threshold voltage (hereinafter, referred to as VTH) of the transistor have changed, and at the same time, the influence is added to variations of the PMOS 521, 531 and the NMOS 522, 532 of the output transistor sections and appears at a signal OUT of the output terminal N503.
Also, in the output buffer circuit 610 of FIG. 2 disclosed in the prior art, the stability of rise time, fall time and signal delay time, etc. of the output signal of an output pad 634 depends on the channel length L and VTH of the final stage transistors PMOS 624a, 626a and NMOS 624b, 626b, and depends as well on the driving capability of the driving circuits 616a, 616b for supplying a signal to the gate end of each of the above-described transistors and the channel length L and VTH of transistors PMOS 620a, 628b and NMOS 620b, 628a. Accordingly, fluctuation in the manufacturing process is reflected in the channel length L and VTH of the final stage transistors PMOS 624a, 626a and NMOS 624b, 626b, as well as in the driving capability of the driving circuits 616a, 616b and the channel length L and VTH of the transistors PMOS 620a, 628b and NMOS 620b, 628a, such that the stability of output operation of the output pad 634 can not be ensured.
FIG. 3 is a schematic waveform diagram showing the change in the output signal upon rising in the conventional output buffer circuit. In FIG. 3, a line Wfast represents the slew rate under a condition that the rising is fast in the conventional output buffer circuit, a line Wslow represents the slew rate under a condition that the rising is slow, a line Wmax represents the maximum slew rate permissible in the PCI, and a line Wmin represents the minimum slew rate permissible in the PCI. As shown in FIG. 3, the slew rate represented by the line Wfast, is greater than the slew rate represented by the line Wmax. As such, in the case of the output buffer circuits shown in FIGS. 1 and 11, there is a problem that the rise time Tr and the fall time Tf of the output signal deviate from the value specified by the PCI standard, according to conditions such as temperature, power supply voltage, etc.
Also, the conventional output buffer circuit 610 shown in FIG. 2, is problematic, in that PMOS 618a, 620a, 628b, NMOS 618b, 620b, 628a, inverters 630a, 630b are needed in addition to the general driving circuits 616a, 616b, such that layout size becomes large and the circuit structure becomes complicated.
An object of the present invention is to provide an output buffer circuit having a divided output transistor, wherein the influence of characteristic variations due to manufacturing process fluctuation and the influence of conditions from change in use such as temperature, power supply voltage are suppressed, and at the same time, a circuit structure is simplified and miniaturized, so that high integration is possible.
An output buffer according to the present invention comprises an output transistor section, and the output transistor section includes an output terminal, a first and a second transistors of the first conductive type of which each one end of source-drain line is connected to a high potential power supply and other end thereof is connected to said output terminal, and a first and a second transistor of the second conductive type of which each one end of source-drain line is connected to a low potential power supply and other end thereof is connected to said output terminal. Also, said output buffer circuit comprises a first transfer gate including a first input terminal to which input signal is inputted and a first driving output terminal to be connected to a gate of said first transistor of the first conductive type and a gate of said second transistor of the second conductive type, and a second transfer gate including a second input terminal to which said input signal is inputted and a second driving output terminal to be connected to a gate of said second transistor of the first conductive type and a gate of said first transistor of the second conductive type. Furthermore, said output buffer circuit comprises a first switch circuit connected between the gate of said second transistor of the first conductive type and said second driving output terminal and including a transfer gate so that conduction thereof is controlled by control signal, and a second switch circuit connected between the gate of said second transistor of the second conductive type and said first driving output terminal and including a transfer gate so that conduction thereof is controlled by control signal. At this time, a driving capability of said second transistor of the first conductive type is larger than that of said first transistor of the first conductive type, and a driving capability of said second transistor of the second conductive type is larger than that of said first transistor of the second conductive type.
In the present invention, an output terminal of the first transfer gate is connected to the gate of the second transistor of the second conductive type via the second switch circuit, and an output terminal of the second transfer gate is connected to the gate of the second transistor of the first conductive type via the first switch circuit. Thereby, when the characteristics of the transistor and use environment are changed, respective operations for making the rise of the output signal of the first and the second transfer gate to be steep and to be smooth are caused at the same time and change of the output signal upon rising of the first and the second transfer gate can be reduced.
Therefore, the output buffer circuit according to the present invention can obtain an effect of suppressing the influence on a signal delay time of the output buffer circuit, rise time, fall time, slew rate, to be small by the connection method of the divided output transistor, even though characteristics such as a channel length of the transistor and threshold voltage are varied due to fluctuations in the process of manufacturing a semiconductor integrated circuit device loaded with the output buffer circuit.
Also, it is possible to adjust the slew rate by a combination of connection of the output transistor section and a minimal addition of elements, and to simplify the structure of the output buffer circuit so that layout area can be reduced, and thereby high integration can be achieved.
Also, it is preferred that conduction of said first and said second switch circuits are controlled synchronously by the same control signal. Furthermore, said first and said second switch circuits may be transfer gates.
Another output buffer circuit according to the present invention comprises an output transistor section, and the output transistor section comprises an output terminal, a first and a second transistors of the first conductive type of which each one end of source-drain line is connected to a high potential power supply and other end thereof is connected to said output terminal, and a first and a second transistor of the second conductive type of which each one end of source-drain line is connected to a low potential power supply and other end thereof is connected to said output terminal. Also, said output buffer circuit comprises a first transfer gate including a first input terminal to which input signal is inputted and a first driving output terminal to be connected to a gate of said first transistor of the first conductive type and a gate of said second transistor of the second conductive type, and a second transfer gate including a second input terminal to which said input signal is inputted and a second driving output terminal to be connected to a gate of said second transistor of the first conductive type and a gate of said first transistor of the second conductive type. At this time, said second transistor of the first conductive type has a larger driving capability than that of said first transistor of the first conductive type, and said second transistor of the second conductive type has a larger driving capability than that of said first transistor of the second conductive type.